A CMOS high-speed wide-range programmable counter
SCIE
SCOPUS
- Title
- A CMOS high-speed wide-range programmable counter
- Authors
- Lee, SH; Park, HJ
- Date Issued
- 2002-09
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGI
- Abstract
- A CMOS high speed wide-range programmable divide-by-N counter was designed and the performance was verified by SPICE simulations and the measurements on the fabricated chip. A new reloading scheme and the use of simplified circuits for three least significant bit flip-flops enabled the high-speed operation of the proposed counter, independently of the number of counter stages. The proposed and Chang's [1] counters were fabricated on the same chip using a 0.6-mum triple-metal CMOS technology. The proposed and Chang's counters with six stages were measured to work up to the clock frequencies of 1.34 GHz and 930 MHz, respectively.
- Keywords
- CMOS integrated circuits; counting circuits; digital circuits; frequency division; frequency synthesizer; high-speed electronics; PRESCALER; DIVIDER
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/18708
- DOI
- 10.1109/TCSII.2002.805627
- ISSN
- 1057-7130
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, vol. 49, no. 9, page. 638 - 642, 2002-09
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