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A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines SCIE SCOPUS KCI

Title
A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines
Authors
Jung, HKLee, SMSim, JYPark, HJ
Date Issued
2010-09
Publisher
IEEK PUBLICATION CENTER
Abstract
By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a 0.18 mu m CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.
Keywords
Crosstalk; crosstalk-induced jitter; transceiver; microstrip; clock timing control; CROSSTALK-INDUCED JITTER; SERPENTINE GUARD TRACE; FAR-END CROSSTALK; REDUCE
URI
https://oasis.postech.ac.kr/handle/2014.oak/17455
DOI
10.5573/JSTS.2010.10.3.232
ISSN
1598-1657
Article Type
Article
Citation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 10, no. 3, page. 232 - 239, 2010-09
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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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