A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS
SCIE
SCOPUS
- Title
- A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS
- Authors
- Kim, B; Yong Liu; Thimothy O. Dickson; John F. Bulzacchelli; Daniel Friedman
- Date Issued
- 2009-12
- Publisher
- IEEE
- Abstract
- A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR). The DFE-IIR receiver uses a single additional IIR filter feedback tap to compensate many postcursors without paying the power and area penalty that would be incurred with a conventional high tap-count DFE. Equalization capabilities of the compact I/O at 10 Gb/s are demonstrated over various channels including conventional chip-to-chip and backplane links with half-baud losses of up to 27 dB. Finally, a transmitter-receiver pair operating over a 40-mm on-chip emulated silicon carrier channel was demonstrated to 8.9 Gb/s, at a link power efficiency of 1.9 mW/Gb/s.
- Keywords
- Backplane channel communication; chip-to-chip communication; compact I/O; continuous-time IIR filter; decision feedback equalizer; serial link; silicon carrier links; DECISION-FEEDBACK EQUALIZATION; 0.13-MU-M CMOS; TRANSCEIVER; TECHNOLOGY; CORE
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/16948
- DOI
- 10.1109/JSSC.2009.2031015
- ISSN
- 0018-9200
- Article Type
- Article
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 44, no. 12, page. 3526 - 3538, 2009-12
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