A novel bias circuit with temperature and process compensation for RFIC

Abstract

Temperature and process variations have become key issues in design of integrated circuits using deep submicron technologies.In the RF front-end circuitry, these characteristics must be compensated to maintain acceptable performance across all process corners and throughout the temperature variations. This article proposes a new bias circuit technique to compensate the variations by adding a single NMOS to the normally bias circuit. A 2.4GHz and 5.2GHz LNAs with the proposed bias circuit have the power gain variation (S21) of only 0.3 dB for the -40 to 85 degrees C temperature range in a 65nm RF CMOS process. (c) 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:26942697, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27170