Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs
SCIE
SCOPUS
- Title
- Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs
- Authors
- Seonhaeng Lee; Kim, C; Kim, H; Kim, GJ; Seo, JH; Son, D; Kang, B
- Date Issued
- 2013-09
- Publisher
- ELESVIER SCIENCE BV
- Abstract
- The effect of a low stress voltage on the negative bias temperature instability degradation in a nanoscale p-channel metal-oxide-semiconductor field-effect transistor using high-k/metal gate stacks is investigated. The direct current-current voltage and carrier separation methods are used to separate the effects of electrons and holes. The results indicate that a high stress voltage generates positive oxide charges that degrade the device, but a low stress voltage generates negative oxide charges that induce the turn-around effect of the threshold voltage. (C) 2013 Elsevier Ltd. All rights reserved.
- Keywords
- DIELECTRICS; DEGRADATION; TRANSISTORS; OXIDES; HFO2; SI
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/14894
- DOI
- 10.1016/J.MICROREL.2013.07.026
- ISSN
- 0026-2714
- Article Type
- Article
- Citation
- Microelectronic Reliability, vol. 53, no. 9-11, page. 1351 - 1354, 2013-09
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