Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications
SCIE
SCOPUS
- Title
- Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications
- Authors
- Sohn, CW; Kang, CY; Baek, RH; Choi, DY; Sagong, HC; Jeong, EY; BAEK, CHANG KI; LEE, JEONG SOO; Lee, JC; Jeong, YH
- Date Issued
- 2012-09
- Publisher
- IEEE
- Abstract
- This letter proposes simple guidelines to design nanoscale fin-based multigate field-effect transistors (FinFETs) for radio frequency (RF)/analog applications in terms of fin height and fin spacing. Geometry-dependent capacitive and resistive parasitics are evaluated using analytic models and are included in a small-signal circuit. It is found that reducing the fin-spacing-to-fin-height ratio of FinFETs, as long as it is compatible with the process integration, is desirable for improving RF performance. This is because the current-gain cutoff frequency and the maximum oscillation frequency are affected by decreasing parasitic capacitance more than by increasing series resistance.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/14734
- DOI
- 10.1109/LED.2012.2204853
- ISSN
- 0741-3106
- Article Type
- Article
- Citation
- IEEE ELECTRON DEVICE LETTERS, vol. 33, no. 9, page. 1234 - 1236, 2012-09
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- There are no files associated with this item.
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