Three-dimensional Simulation of Dopant Fluctuation Induced Threshold Voltage Dispersion in Non-planar MOS Structures Targeting Flash EEPROM Transistors
SCIE
SCOPUS
- Title
- Three-dimensional Simulation of Dopant Fluctuation Induced Threshold Voltage Dispersion in Non-planar MOS Structures Targeting Flash EEPROM Transistors
- Authors
- Kim, B; Kwon, W; Baek, CK; Jin, S; Song, Y; Kim, DM
- Date Issued
- 2008-06
- Publisher
- IEEE
- Abstract
- Threshold voltage (V-T) dispersion due to random discrete dopant fluctuation was simulated in recessed-channel, triple-gate, and saddle MOS structures, targeting future floating-gate memory cell transistor. All nonplanar structures showed improved V-T dispersion characteristics, compared with the planar type by proper adjustment of the tunnel oxide structure and channel doping level. The recessed-channel showed a continuous improvement of V-T dispersion with the channel area widening beyond a certain threshold recess depth. In triple-gate structure, a significant reduction in V-T dispersion is shown possible primarily via the superior gate controllability. Among the nonplanar structures, the saddle structure yielded the lowest V-T variation for a fixed target V-T with the choice of moderate device parameters from the other structures.
- Keywords
- density-gradient (DG) model; FinFET; flash EEPROM cell; gummel iteration; nonplanar MOS; random discrete dopant fluctuation (DDF); RC-FinFET; recess-channel-array transistor (RCAT); recessed-channel; saddle; threshold voltage distribution; triple-gate; MOSFETS; MEMORY; OXIDE; GATE
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/13714
- DOI
- 10.1109/TED.2008.921988
- ISSN
- 0018-9383
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 55, no. 6, page. 1456 - 1463, 2008-06
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- There are no files associated with this item.
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