Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells
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SCOPUS
- Title
- Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells
- Authors
- Baek, CK; Kim, B; Quan, WY; Kwon, W; Park, YJ; Min, HS
- Date Issued
- 2005-01
- Publisher
- The Japan Society of Applied Physics
- Abstract
- We present an efficient design technique for implementing the optimal ramped gate soft-programming for curing the over-erased flash EEPROM cells. The technique does not rely on any I-V model but is solely based upon using the actual cell performance data and enables accurate prediction of programming time, given supply current (I-S). The full utilization of available supply current renders the programming speed much faster and also enables reliable multi-bit soft-programming, The ramped gate scheme induces a strong self-con vergence of the simultaneously up-shifted threshold voltages regardless of their initial values or the variations of the shift speed from cell to cell.
- Keywords
- ramped gate soft-programming; multi-bit soft-programming; over-erase
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/13710
- DOI
- 10.1143/JJAP.44.L578
- ISSN
- 0021-4922
- Article Type
- Article
- Citation
- JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, vol. 44, no. 16, page. L578 - L580, 2005-01
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