High Speed, Low Power Programming in 0.17mum Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects
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- Title
- High Speed, Low Power Programming in 0.17mum Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects
- Authors
- Baek, CK; Song, YH; Kim, B; Quan, WY; Park, YJ; Min, HS; Kim, DM
- Date Issued
- 2004-02-01
- Publisher
- The Japan Society of Applied Physics
- Abstract
- We present a fast low power programming in floating gate electrically erasable and programmable read only memory (EEPROM) cells with the aspect ratio of 0.09 / 0.17 mum. The threshold voltage shift (Delta V-TH) of 5V, for example, was done in less than I mus, using the peak drain current (I-D) of approximate to100muA. More importantly, by using the substrate bias (V-B), programming was done in 2-3 mus at I-D of 30 muA and V-D of 3V. This observed speed is faster than reported values by about 2.5 and power used was about 50% lower than the previous one. The optimal programming bias conditions are presented, together with the reasons for fast programming.
- Keywords
- NOR-type flash EEPROM; low power programming; substrate bias effect; drain turn-on; high speed programming; VLSI MOSFETS; PART I; EEPROM
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/13707
- DOI
- 10.1143/JJAP.43.L224
- ISSN
- 0021-4922
- Article Type
- Article
- Citation
- JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS, vol. 43, no. 2A, page. L224 - L226, 2004-02-01
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