The Effects of Channel Length, Width, and Recovery on Negative Bias Temperature Instability in p-MOSFETs with Ultra-thin Gate Dielectrics

Abstract

This thesis describes the effect of negative bias temperature instability (NBTI) on reliability of p-MOSFETs with ultra-thin gate dielectrics. The effects of channel length L and width W on NBTI degradation of a MOSFET with a pure SiO2 gate oxide fabricated using the 65-nm dual gate CMOS technology were investigated. The mechanism for the recovery of the NBTI degradation in a SiON p-MOSFET was also described.NBTI affects p-MOSFETs differently, depending on L. Short-channel (SC) MOSFETs (0.078 ≤ L ≤ 0.46 μm) show less NBTI degradation with decreasing L

this trend was attributed to build-up of negative oxide charge -Qot due to boron-related electron traps by breaking off the hydrogen from B-H bonds in the gate-drain (G-D) overlap region. The B-H bonds in SC devices with SiO2 gate dielectric are considered to originate from boron diffusion in the source/drain (S/D) extension region. Experimental results indicate that NBTI-induced oxide traps in the G-D overlap region are negatively charged in SiO2 p-MOSFET and positively charged in SiON p-MOSFET. For SC MOSFETs, the effect of negative oxide charge should be taken importantly when evaluating NBTI degradation, because of the increased ratio of the S/D overlap region to L. In long channel (LC) MOSFETs (0.46 ≤ L ≤ 10 μm), NBTI degradation increased as L decreased, because of the mechanical stress in the channel region induced by the SiN capping layer. Changes in carrier mobility indicate that stress components were compressive in SC devices, and tensile in LC devices. Device reliability is degraded more by compressive stress than by tensile stress, because of the narrowing of the Si channel bandgap due to the compressive SiN capping layer.The effect of W on NBTI of p-MOSFET with an ultra-thin SiO2 gate dielectric was reported. Irrespective of channel length, NBTI degradation increased as W decreased, because of the mechanical stress induced by the STI (Shallow Trench Isolation) and SiN capping layer.The recovery property of NBTI degradation was investigated for a p+ poly-Si gate p-MOSFET with an SiON gate oxide. Experimental results indicate that the recovery of the NBTI degradation occurs due to electrical neutralization of the NBTI-induced positive charges at the SiON/Si interface and in the gate dielectric. The neutralization of interface charges by electrons was a fast process that occurred just after the device returned to the recovery state. The neutralization of positive charges in the gate dielectric was a slow process associated with the injection of electrons into gate dielectric. Below the flat-band voltage, the amount of the recovery increased as the gate voltage Vg at the recovery state increased. A further increase of Vg did not affect the amount of the recovery. These experimental results demonstrate that the major cause of the recovery is a neutralization of the NBTI-induced positive charges by electrons, instead of a hydrogen passivation of the defect sites.