1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
- Title
- 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
- Authors
- Lee, Seon Kyoo; Kim, Hyun-Jin; Lim, Jeong-Don; Lee, Jang-Woo; Na, Dae-Hoon; Shin, Joon-Ho; Kim, Chae-Hoon; Yu, Seung-Woo; Shin, Ji-Yeon; Lee, Seon-Kyoo; Rajagopal, Devraj; Kim, Sang-Tae; Kang, Kyeong-Tae; Park, Jeong-Joon; Kwon, Yong-Jin; Lee, Min-Jae; Kim, Sung-Hoon; Shin, Seung-Hoon; Kim, Hyung-Gon; Kim, Jin-Tae; Kim, Ki-Sung; Joo, Han-Sung; Park, Chan-Jin; Kim, Jae-Hwan; Lee, Man-Joong; Kim, Do-Kook; Yang, Hyang-Ja; Byeon, Dae-Seok; Park, Ki-Tae; Kyung, Kye-Hyun; Choi, Jeong-Hyuk
- Date Issued
- 2015-02-22
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Abstract
- NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and high-throughput performance. In recent years, a SATA interface supporting only up to 600MB/S throughput has hindered the accelerating performance growth of SSDs due to the host bandwidth limit. A PCI Express (PCIe) has emerged to close the limit because it can deliver 1GB/s throughput per lane and can be scaled to multi-lane to improve bandwidth [1]. Accordingly, the SSD performance bottleneck has moved from the host interface to the NAND flash interface. In a memory system, a die-stacking technology in a NAND flash multi-chip package (MCP) effectively increases capacity and throughput performance in terms of PCB complexities and power consumption compared to a method increasing the number of channels. However, the multi-drop bus topology on NAND interfaces severely affects I/O speed degradations due to channel reflections and inter-symbol interference (ISI) resulting from large capacitive loadings [2]. The undeniable paradox between larger storage capacity and higher I/O bandwidth has become a key challenge to reach enterprise-class SSDs. To overcome this issue, this paper presents a frequency-boosting interface chip (F-Chip) to boost I/O speeds while meeting capacity requirements. A 2Tb NAND flash MCP with 1GB/s toggle DDR interface is accomplished by incorporating the F-Chip into the NAND MCP including a 16-die stacked 128Gb NAND flash [3].
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/118864
- Article Type
- Conference
- Citation
- 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers, page. 138 - 139, 2015-02-22
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