A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate
- Title
- A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate
- Authors
- Lee, Seon Kyoo; Lee, Seungjae; Lee, Jin-Yub; Park, Il-Han; Park, Jongyeol; Yun, Sung-Won; Kim, Min-Su; Lee, Jong-Hoon; Kim, Minseok; Lee, Kangbin; Kim, Taeeun; Cho, Byungkyu; Cho, Dooho; Yun, Sangbum; Im, Jung-No; Yim, Hyejin; Kang, Kyung-Hwa; Jeon, Suchang; Jo, Sungkyu; Ahn, Yang-Lo; Joe, Sung-Min; Kim, Suyong; Woo, Deok-Kyun; Park, Jiyoon; Park, Hyun-Wook; Kim, Youngmin; Park, Jonghoon; Choi, Yongsu; Hirano, Makoto; Ihm, Jeong-Don; Jeong, Byunghoon; Lee, Seon-Kyoo; Kim, Moosung; Lee, Hokil; Seo, Sungwhan; Jeon, Hongsoo; Kim, Chan-Ho; Kim, Hyunggon; Kim, Jintae; Yim, Yongsik; Kim, Hoosung; Byeon, Dae-Seok; Yang, Hyang-Ja; Park, Ki-Tae; Kyung, Kye-Hyun; Choi, Jeong-Hyuk
- Date Issued
- 2016-02-02
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Abstract
- NAND flash memory is widely used as a cost-effective storage with high performance [1-2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective storage device. This paper also introduces several approaches to compensate for reliability and performance degradations caused by the 14nm transistors and the 150 cells/string structure. A technique was developed to suppress the background pattern dependency (BPD) by applying a low voltage to upper word lines (WLs) - the drain side(SSL side) WLs with respect to the location of the selected WL - during the verify sequence. Two techniques are also used to improve the program performance: equilibrium pulse scheme and smart start bias control scheme (SBC) in the MSB page. In addition, the first cycle recovery (FCR) of read enable (RE) and the bi-directional data strobe (DQS) is used to achieve a high speed I/O rate. As a result, a 640μs program time and a 800MB/s I/O rate is achieved.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/118863
- Article Type
- Conference
- Citation
- 63rd IEEE International Solid-State Circuits Conference, ISSCC 2016, page. 138 - 139, 2016-02-02
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