A study on the electrical characteristics of 2D material-based band modulation FET
- Title
- A study on the electrical characteristics of 2D material-based band modulation FET
- Authors
- 이준호
- Date Issued
- 2023
- Publisher
- 포항공과대학교
- Abstract
- As the 4th industry develops, the demand for IoT devices in various applications is increasing. In the future, in order for IoT devices to deal with large amounts of data, low-power operating devices will be required. A conventional Metal Oxide Silicon Field Effect Transistor (MOSFET) operated by thermionic emission has a subthreshold swing (SS) value limit of 60 mV/dec, so it is difficult to reduce overall power consumption by scaling the supply voltage. On the other hand, steep switching devices have a low SS value and are advantageous for low-power operation by reducing the supply voltage without improving the off-current. Among them, band modulation FET or Feedback Field Effect Transistor (FB-FET) is being studied because it has a high Ion/Ioff and a very small SS value by using a positive feedback mechanism. Recently, study on FB-FET, which has improved characteristics by scaling the Si channel thickness to 7 nm in 28 nm FDSOI (Fully Depleted Silicon On Insulator), has been conducted. However, the mobility of the silicon degrades from a channel thickness of 5 nm or less, and a new channel material is needed to replace it.
In this study, FB–FET was fabricated using WSe2 as a channel and its electrical characteristics were analyzed. For the improvement of the positive feedback mechanism, the structure of the FB-FET was proposed by introducing the front gate, buried gate and pn-homojunction WSe2. When the front gate voltage (VFG) was changed with the drain voltage (VD) of 1 V and the buried gate voltage (VBG) of 0 V applied, the drain current steeply increased near 0 V and had an SS value of 158 mV/dec despite the use of a 30 nm thick Al2O3 dielectric film. According to simulation results scaling the EOT (Equivalent Oxide Thickness) of the dielectric film, there is a tendency for the threshold voltage to shift, the on-current to rise, and the SS value to reduce. An inverter circuit was simulated using p-FBFET instead of PMOS from HSPICE simulation. The simulation result of this shows that power consumption is reduced by about 25.4% with a gain about 5 times higher than conventional CMOS. This is expected to be applied to various fields requiring low power operations.
- URI
- http://postech.dcollection.net/common/orgView/200000660894
https://oasis.postech.ac.kr/handle/2014.oak/118337
- Article Type
- Thesis
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