A 384G Output NonZeros/J Graph Convolutional Neural Network Accelerator
SCIE
SCOPUS
- Title
- A 384G Output NonZeros/J Graph Convolutional Neural Network Accelerator
- Authors
- Lee, Kyeong-Jun; Moon, Seunghyun; Sim, Jae-Yoon
- Date Issued
- 2022-10
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Abstract
- This brief presents the first IC implementation of graph convolutional neural network (GCN) accelerator chip. A sparsity aware dataflow optimized for sub-block-wise processing of three different matrices in GCN is proposed to improve the utilization ratio of computing resources while reducing the amount of redundant access of off-chip memory. The implemented accelerator in 28-nm CMOS produces 384G NZ outputs/J for the extremely sparse matrix multiplications of the GCN. It shows 58k-to-143k, 38k-to-92k and 5k-to-13k Graph/J for the benchmark graph datasets of Cora, Citeseer and Pubmed, respectively. The energy efficiency in Graph/J of the proposed 16b ASIC implementation shows about 4-to-11x and 8-to-25x improvements compared to the previously reported 8b FPGA and 32b FPGA implementations, respectively.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/117872
- DOI
- 10.1109/TCSII.2022.3188428
- ISSN
- 1549-7747
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 69, no. 10, page. 4158 - 4162, 2022-10
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