Open Access System for Information Sharing

Login Library

 

Thesis
Cited 0 time in webofscience Cited 0 time in scopus
Metadata Downloads

Approximate division and square root circuit designs

Title
Approximate division and square root circuit designs
Authors
김두환
Date Issued
2022
Publisher
포항공과대학교
Abstract
This paper proposes a series of approximate divider and square root circuit designs with high accuracy, low latency, low area, and low power dissipation requirements. The proposed designs are constructed using an array of subtractor with multiplexer or controlled add-subtract cell elements, with both exact and approximate versions. The utility of the proposed designs are evaluated by utilizing them in some example image processing application such as change detection and foreground extraction for division and contrast enhancement for square root, with demonstrably satisfactory results and large peak signal-to-noise ratios and structural similarity values. The accuracy and hardware characteristics of the proposed arithmetic designs are also analyzed and compared with an accurate designs as well as previously proposed state-of-theart approximate designs. The results show that the largest 16/8 approximate divider has a Mean Relative Error Distance (MRED) of 6.30x10−4 to 1.91x10−2, Normalized Mean Error Distance (NMED) of 2.60x10−4 to 1.15x10−2, and Root Mean Squared Error (RMSE) of 0.185 to 2.441 with 67.2% of the area, 55.5% of the power usage, and 56.2% of the propagation delay when compared to a completely accurate design. When compared to previous state-of-the-art designs, the proposed design had the best hardware characteristics, in terms of delay, area, and power usage. When applied to a 16-bit radicand (the number under the square root symbol), the proposed square root designs have the lowest error rates, normalized mean error distances, and mean relative error distances by at least 1.8x, when compared to all previous methods using the same number of approximate cells. When evaluated using designs synthesized using Synopsys Design Compiler with a 28nm process, the delay, area, power, and powerdelay-product characteristics outperform all previous designs in all but a few cases. These results demonstrate that the proposed designs permit the use of a flexible range of approximate designs with varying accuracy and hardware overhead characteristics, and a suitable design can be selected based on the user design requirements.
URI
http://postech.dcollection.net/common/orgView/200000601815
https://oasis.postech.ac.kr/handle/2014.oak/117158
Article Type
Thesis
Files in This Item:
There are no files associated with this item.

qr_code

  • mendeley

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Views & Downloads

Browse