Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications
SCIE
SCOPUS
- Title
- Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications
- Authors
- Mun, Han-Gyeol; Moon, Seunghyun; Kim, Byungjun; Lee, Kyeong-Jun; Sim, Jae-Yoon
- Date Issued
- 2023-02
- Publisher
- Institute of Electrical and Electronics Engineers
- Abstract
- State-of-the-art compact models such as MobileNets and EfficientNets are structured using a linear bottleneck and inverted residuals. Hardware architecture using a single dataflow strategy fails to balance the required memory bandwidth with the given computational resources. This work presents a heterogeneous dual-core accelerator that performs a block-wise pipelined process as a unit using a bottleneck-stationary (BS) dataflow. The BS greatly relieves the requirement on DRAM bandwidth and on-chip SRAM capacity. A look-behind-only attention is also proposed as a co-optimized algorithm. Compared to the state-of-the-art hardware scheme, the proposed accelerator demonstrates a reduction of 1.8-2.9 in latency and 2.2-3 in energy consumption, respectively.For verification, the accelerator with a 16-bit integer precision was implemented using 28nm CMOS process. Measurements show energy efficiencies of 0.5-to-3.75 TOPS/W in a supply voltage range of 0.55-to-1.15V. IEEE
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/115381
- DOI
- 10.1109/tcsi.2022.3222862
- ISSN
- 1549-8328
- Article Type
- Article
- Citation
- IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 2, page. 772 - 782, 2023-02
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