Techniques for Easier Design of A High-Speed Feed-Forward Equalizing Transmitter

Abstract

To ease high-speed link design by resolving conflicting design requirements (high-speed, low power, and small area) and automate manual physical design, (1) a coefficient-error robust feed-forward equalizing (FFE) transmitter (TX) architecture, and (2) a framework for development of a layout generator are proposed. Massively parallel links incorporating FFE TXs are one of popular solutions to implement high-speed and power-efficient data communication, but are vulnerable to PVT (Process, Voltage, Temperature) variation, and so have a penalty from large calibration overheads. However, the proposed FFE TX can reduce calibration overheads of massively parallel links, and so efforts in design specification for a high-speed, power-efficient, and compact data link can be saved. With the proposed framework, an analog/mixed-signal layout generator can be developed to automate manual physical design of high-speed link, and layout generations of FFE TX are demonstrated at multiple technology nodes.

The proposed FFE TX improves its robustness to a coefficient error and its power efficiency by utilizing a high-pass digital difference filter and a channel loss to attenuate the effects of the coefficient errors. To verify the proposed FFE architecture, the conventional and the proposed FFEs were fabricated in 65 nm CMOS technology and tested eye sensitivity and eye variation at 8 Gb/s on 25 dB, 13.2 dB, and 9.6 dB PCB traces. Compared to the conventional FFE TX, the proposed FFE TX improves the eye sensitivity and the eye variation by about more than 230% on a 25-dB lossy channel without calibration. In addition, this improvement increases as the channel loss increases. The proposed FFE TX also improves the power efficiency by 230% at 25% utilization on a 25-dB lossy channel. These results imply that the proposed FFE Tx can reduce calibration circuits in a massively parallel links and the power consumption.

The first FFE SST TX layout generator was developed by the proposed framework including a GUI-based template engine, and generated seven different DRC/LVS-clean TXs in multiple technologies: one TX in 40-nm, three TXs in 65-nm, and three TXs in 90-nm CMOS technology. Three 65-nm TXs was fabricated and tested. In post-layout simulation with 20-dB channels, 40-nm TX achieved data rate of 36 Gb/s and three 90-nm TXs achieved data rates of 10 Gb/s, 7 Gb/s, and 5 Gb/s, respectively. In measurement, one 65-nm TX achieved data rates of 6 Gb/s on a 20-dB PCB trace with 27-dB depth notch at 1.5 GHz, and 8 Gb/s on a 20-dB PCB trace. The other two 65-nm TXs also achieved data rates of 10 Gb/s, 14 Gb/s on 20-dB PCB traces, respectively. Total generation time was less than 5 days, including iterative parameter tuning by a human designer and computation (30 minutes for TX core, 8 hours for power network). Fast post-layout analysis of TX’s performance-power trade-off was enabled by the presented generator for the first time.

These results imply that the coefficient-error robust feed-forward equalizing FFE TX, and the framework for development of a layout generator can ease design of a high-speed, power-efficient, and compact FFE TX, and so are promising solutions to design a high-speed, power-efficient, and compact link.