Design and Fabrication of Pseudo-CMOS Gate Arrays Based on a-IGZO Thin-Film Transistors

Abstract

With the advancement of thin-film transistor (TFT) technologies, the functionality and degree of integration of TFT-based integrated circuits (ICs) have increased. In other words, TFT-based ICs become closer to commercialization. A combination of gate arrays and digital printing techniques such as inkjet-printing is a promising design approach for fabricating TFT-based ICs. A gate array is a prefabricated chip having non-functional transistor array or logic gate array. On a gate array, interconnects are printed to make ICs. This design approach has attracted much attention due to its low development cost and short prototype turnaround time. However, previous works are far from commercialization. To become closer to commercialization, a gate array is required to be fabricated using high-end TFT technologies and an interconnect technique has to achieve as small size as possible. In this work, a gate array is fabricated using a-IGZO TFTs and pseudo-CMOS logics that have been widely used to fabricate TFT-based ICs. Furthermore, laser-induced forward transfer (LIFT) is used as an interconnect technique due to its potential for very small feature size. The gate array is composed of mainly pseudo-CMOS NOR gates with a structure proposed in this work. The structure increases device density while resulting in small reduction of static noise margin compared to the conventional structure. The gate array is designed to prevent a problem that can arise when a NOT gate is configured with a NOR gate. In parallel with the gate array work, LIFT is investigated as a interconnect technique and LIFT lines are optimized. Finally, various digital circuits are configured on the gate array with the optimized LIFT interconnects and demonstrated successfully, which shows availability of the gate array with LIFT.