A 87.5-dB-SNDR Residue-integrated SAR ADC with a Digital-domain Capacitor Mismatch Calibration
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- Title
- A 87.5-dB-SNDR Residue-integrated SAR ADC with a Digital-domain Capacitor Mismatch Calibration
- Authors
- KU, HWANSEOK; Seungnam Choi; SIM, JAE YOON
- Date Issued
- 2021-04
- Publisher
- 대한전자공학회
- Abstract
- This paper presents an asynchronous-clocking 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) suitable for high-precision sensor applications. Comparator noise and nonlinearity from capacitor mismatch, as two major performance-limiting problems of SAR ADC, are resolved by noise averaging with a residue integration and a digital-domain capacitor error calibration, respectively. The proposed ADC is implemented using 180-nm CMOS technology in an area of 0.68㎟. The calibration improves SNDR by 5.9 dB and SFDR by 14.3 dB, achieving an SNDR of 87.5 dB and an SFDR of 106.85 dB, respectively.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/110089
- DOI
- 10.5573/JSTS.2021.21.2.143
- ISSN
- 1598-1657
- Article Type
- Article
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 21, no. 2, page. 143 - 151, 2021-04
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