GUI-Enhanced layout generation of FFE SST TXs for fast high-speed serial link design
- Title
- GUI-Enhanced layout generation of FFE SST TXs for fast high-speed serial link design
- Authors
- KIM, BYUNGSUB; CHANHO, KIM; PARK, HONG JUNE; HAN, SEUNGHO; JEONG, SUNGYU
- Date Issued
- 2020-07-20
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Abstract
- We present the first FFE SST TX layout generator enhanced by various software techniques including a GUI-based template engine. Seven different DRC/LVS-clean TXs were generated in multiple technologies (40nm/65nm/90nm CMOS) for the first time, and achieved adequate maximum data rates: 36Gb/s with 40nm in post-layout simulation; 14Gb/s with 65nm in measurement. Total generation time was less than 5 days, including iterative parameter tuning by a human designer and computation (30 minutes for TX core, 8 hours for power network). Fast post-layout analysis of TX's performance-power trade-off was enabled by the presented generator for the first time.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/106102
- Article Type
- Conference
- Citation
- 57th ACM/IEEE Design Automation Conference, DAC 2020, 2020-07-20
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