An 8.8-GS/s 6-bit CMOS time-interleaved flash analog-to-digital converter with multi-phase clock generator
SCIE
SCOPUS
- Title
- An 8.8-GS/s 6-bit CMOS time-interleaved flash analog-to-digital converter with multi-phase clock generator
- Authors
- Jang, YC; Bae, JH; Park, SH; Sim, JY; Park, HJ
- Date Issued
- 2007-06
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Abstract
- An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-mu m CMOS process. Eight uniformly-spaced 1.1 GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0 bits was measured to be 1.2 GHz. The chip area and power consumption were 2.24 mm(2) and 1.6 W, respectively.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/10293
- DOI
- 10.1093/IETELE/E90-C.6.1156
- ISSN
- 0916-8524
- Article Type
- Article
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, vol. E90C, no. 6, page. 1156 - 1164, 2007-06
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- There are no files associated with this item.
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