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CMOS sense-amplifier type flip-flop having improved setup/hold margin SCIE SCOPUS

Title
CMOS sense-amplifier type flip-flop having improved setup/hold margin
Authors
Cho, SIHeo, JSPark, HJPark, MHKim, YH
Date Issued
2003-12
Publisher
IEICE-INST ELECTRONICS INFORMATION CO
Abstract
A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.
URI
https://oasis.postech.ac.kr/handle/2014.oak/10281
ISSN
0916-8524
Article Type
Article
Citation
IEICE TRANSACTIONS ON ELECTRONICS, vol. E86C, no. 12, page. 2508 - 2510, 2003-12
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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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