A low-power half-swing clocking scheme for flip-flop with complementary gate and source drive
SCIE
SCOPUS
- Title
- A low-power half-swing clocking scheme for flip-flop with complementary gate and source drive
- Authors
- Kim, JC; Lee, SH; Park, HJ
- Date Issued
- 1999-09
- Publisher
- IEICE-INST ELECTRONICS INFORMATION CO
- Abstract
- A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS hip-flop to reduce the power consumption of the clock system by 43%, while keeping the hip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-hop using this scheme is less than half of that using the previous half-swing clocking scheme.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/10270
- ISSN
- 0916-8524
- Article Type
- Article
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, vol. E82C, no. 9, page. 1777 - 1779, 1999-09
- Files in This Item:
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