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전체 가 나 다 라 마 바 사 아 자 차 카 타 파 하

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Showing results 1 to 14 of 14

Article

Bottom oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm NodeSCIESCOPUS

IEEE ACCESS, vol. 7, page. 75762 - 75767, 2019-06

Conference

Comparison of virtual source velocity and apparent mobility in shrunk Lg=15 nm n/p-SNWFETs with various channel diameters

the 17th International Nanotech Symposium & Exhibition, 2019-07-04

Conference

Critical dimension variations of sub 5-nm node fin and nanosheet FETs

the 17th International Nanotech Symposium & Exhibition, 2019-07-03

Article

DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect TransistorsSCIESCOPUS

IEEE ACCESS, vol. 10, page. 22032 - 22037, 2022-02

Conference

Geometric Optimization of Silicon Gate-All-Around Field-Effect Transistors (GAAFETs) for DC/AC Performances

제1회 반도체공학회 학술대회, 2018-12-21

Conference

Impact of Thermo-Mechanical Stress Induced by Through-Silicon Vias on Performance Variations of 5-nm Node Si-Nanosheet FETs

the 17th International Nanotech Symposium & Exhibition, 2019-07-04

Article

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact SchemesSCIESCOPUS

IEEE ACCESS, vol. 9, page. 138192 - 138199, 2021-10

Article

Nanowire Diameter Dependency of the Variability in n/p Silicon Nanowire FETs With Ultrashort Gate Length of 15 nmSCIESCOPUS

IEEE Transactions on Electron Devices, vol. 69, no. 12, page. 6529 - 6534, 2022-12

Conference

Observation of Mobility and Velocity as Channel Diameter Change in the Shrunk Lg = 18nm Silicon Nanowire MOSFETs

제1회 반도체공학회 학술대회, 2018-12-21

Conference

Observation of Mobility and Velocity Behaviors in Ultra Scaled Lg=15 nm Silicon Nanowire pMOSFETs with Different Channel Diameters

제26회 한국반도체학술대회 (KCS 2019), 2019-02-15

Article

Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETsSCIESCOPUS

IEEE Journal of the Electron Devices Society, vol. 6, no. 1, page. 942 - 947, 2018-08

Article

TCAD-Based Flexible Fin Pitch Design for 3-nm Node 6T-SRAM Using Practical Source/Drain Patterning SchemeSCIESCOPUS

IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 68, no. 3, page. 1031 - 1036, 2021-03

Conference

The Effects of Realistic U-shaped Source/Drain on DC/AC Performances of Silicon Nanosheet FETs for Sub 5-nm Node SoC Applications

2019 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), page. 133 - 135, 2019-03-14

Conference

Vth Variation Induced by S/D Mole Fraction and Si/SiGe Intermixing of Si-NSFETs

제26회 한국반도체학술대회 (KCS 2019), 2019-02-14

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Browsing by AuthorLee, Seunghwan

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