Open Access System for Information Sharing

Login Library
검색

  Browse by Researchers
PARK, HONG JUNE(박홍준) scopus
Department
Dept of Electrical Engineering(전자전기공학과)
Major(s)
-

Co-researchers

    Keyword

    Publication & Time Cited Count (For the Last 5 years)

    Results 101-116 of 116 (Search time: 0.001 seconds).
    Export
    Applied search limites :
    Date Issued : [2010 TO 2019]
    Conference
    A 0.63ps Resolution, 11b Pipeline TDC in 0.13μm CMOS

    Symposium on VLSI Circuits, page. 152 - 153, 2011-06-16

    Conference
    A 0.63ps Resolution, 11b Pipeline TDC in 0.13um CMOS

    Symp. on VLSI Circuits, 2011-06-14

    Conference
    A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping TDC

    SOVC2011, 2011-05-28

    Conference
    A 0.1-fref BW 1GHz Fractional-N PLL with FIR-Embedded Phase-Interpolator-Based Noise Filtering

    IEEE International Solid-State Circuits Conference, page. 94 - 95, 2011-02-21

    Conference
    A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering

    ISSCC 2011, 2011-02-20

    Conference
    A Transmitter with Different Output Timing to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines

    International SoC Design Conference, page. 364 - 367, 2010-11-23

    Conference
    A Transmitter with Different Output Timing to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines

    SoC Design Conference (ISOCC), 2010 International, 2010-11-22

    Conference
    A Crosstalk-and-ISI Equalizing Receiver in 2-Drop Single-Ended SSTL Memory Channel

    IEEE Custom Integrated Circuits Conference, 2010-09-21

    Conference
    A Slew-Rate Controlled Transmitter to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines

    IEEE Custom Integrated Circuits Conference, 2010-09-20

    Conference
    A Slew-Rate Controlled Transmitter to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines

    Custom Integrated Circuits Conference, 2010-09-20

    Conference
    A Crosstalk-and-ISI Equalizing Receiver in 2-Drop Single-Ended SSTL Memory Channel

    CICC, 2010-09-19

    Conference
    TX Digital Circuit for USB 2.0 PHY High Speed Interface

    2010 International Conference on Electronics, Information, and Communication, 2010-07-01

    Conference
    Digital Circuit of USB 2.0 PHY High Speed RX Interface

    2010 International Conference on Electronics, Information, and Communication, 2010-07-01

    Conference
    A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

    SID Symposium Digest of Technical Papers, 2010-05-30

    Conference
    A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

    Society for Information Display 2010, page. 62 - 65, 2010-05-25

    Conference
    A 1GHz ADPLL with a 1.25ps Minimum-Resolution Sub-Exponent TDC in 0.18um CMOS

    International Solid-State Circuits Conference, 2010-02-10

    1 2 3 4 5 6
    개인정보처리방침 Personal Information Protection Policy

    library@postech.ac.kr Tel: 054-279-2548

    Copyrights © by 2017 Pohang University of Science ad Technology All right reserved.

    Browse

    Login Library Help