Electrical Characterization of ReRAM Devices for High-Density Memory Applications

Abstract

Conventional charge-based memories such as NAND, NOR Flash memory, and DRAM have faced scalability limit due to severe cross-talk, noise, and 6F2 structure. To solve the limitations and problems, several emerging non-volatile memories: phase-change memory (PRAM), magnetic memory (MRAM), and resistive memory (ReRAM) have been investigated to be alternative techniques. Among these candidates, particularly, the ReRAM has been extensively investigated due to high scalability (4F2), low power consumption, high speed operation, CMOS compatibility, and simple structure. However, ReRAM suffers from poor switching uniformity in terms of set voltage, reset voltage, low-resistance state (LRS), and high-resistance state (HRS). During switching cycles, the device requires different operating voltage and switching current was always abnormally changed. It can induce severe writing and sensing failure in high-density memory. Furthermore, leakage current is an additional severe problem in cross-point array structure. During reading HRS cell, leakage current are coming from unselected LRS cells and these leakage currents are accumulated to HRS current of the selected bit-line. Once sum of HRS current and total leakage current is larger than LRS current, reading operation of cross-point array can be failed. Therefore, in this thesis, the author had investigated various analyses such as a defect engineering and structural engineering to obtain the reliable switching and retention of the ReRAM. The author observed the defect and structure of the device are highly important parameters to form filament and to dissolve filament. The author found that the switching parameters of the device are correlated each other, and its understanding is a key solution for ReRAM reliability. In addition to the switching reliability, to implement high-density cross-point array structure, non-linear ReRAM, e.g. the selector-less ReRAM had been investigated due to its low leakage current, simple structure, and reliable switching. Finally, the author simulated and calculated ReRAM cross-point array with realization of 1Mb cross-point array. To obatain simulation parameters, the ReRAM cross-point array was fabricated at 8 inch wafer using NNFC and Dongbu hightek incorporation. Not only devices and fabrication processes, but also sensing and writing operations were implemented in peripheral regions. Thus, the author could observe important device parameters for cross-point array reliability with cell and peripheral interface of cross-point array. This thesis will be guideline of ReRAM research and development for cross-point memory array.