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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 이정수 | - |
| dc.date.accessioned | 2018-06-18T11:19:23Z | - |
| dc.date.available | 2018-06-18T11:19:23Z | - |
| dc.date.created | 2014-08-05 | - |
| dc.date.issued | 2014-07-02 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/67148 | - |
| dc.publisher | Nano Korea symposium | - |
| dc.relation.isPartOf | The 12th Nano Korea symposium | - |
| dc.title | Effects of Grain Boundary Traps on Electrical Variation in 3D Vertical NAND Flash Memory Cell with Macaroni Channel Structure | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | The 12th Nano Korea symposium | - |
| dc.citation.conferenceDate | 2014-07-02 | - |
| dc.citation.conferencePlace | KO | - |
| dc.citation.title | The 12th Nano Korea symposium | - |
| dc.contributor.affiliatedAuthor | 이정수 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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Related Researcher
- 이정수LEE, JEONG SOO
- Dept of Electrical Enginrg