DC Field | Value | Language |
---|---|---|
dc.contributor.author | 심재윤 | - |
dc.contributor.author | 여동희 | - |
dc.contributor.author | 성기환 | - |
dc.contributor.author | 전성환 | - |
dc.contributor.author | 김종훈 | - |
dc.contributor.author | 박홍준 | - |
dc.date.accessioned | 2018-06-18T03:34:24Z | - |
dc.date.available | 2018-06-18T03:34:24Z | - |
dc.date.created | 2012-03-23 | - |
dc.date.issued | 2011-06-22 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/60504 | - |
dc.publisher | International Technical Conference on Circuits/Systems, Computers and Communications | - |
dc.relation.isPartOf | International Technical Conference on Circuits/Systems, Computers and Communications | - |
dc.relation.isPartOf | ITC-CSCC | - |
dc.title | Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | International Technical Conference on Circuits/Systems, Computers and Communications | - |
dc.citation.conferenceDate | 2011-06-19 | - |
dc.citation.conferencePlace | KO | - |
dc.citation.title | International Technical Conference on Circuits/Systems, Computers and Communications | - |
dc.contributor.affiliatedAuthor | 심재윤 | - |
dc.contributor.affiliatedAuthor | 여동희 | - |
dc.contributor.affiliatedAuthor | 성기환 | - |
dc.contributor.affiliatedAuthor | 전성환 | - |
dc.contributor.affiliatedAuthor | 김종훈 | - |
dc.contributor.affiliatedAuthor | 박홍준 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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