DC Field | Value | Language |
---|---|---|
dc.contributor.author | 백록현 | - |
dc.contributor.author | 김태우 | - |
dc.contributor.author | T.Michalak | - |
dc.contributor.author | C.Borst | - |
dc.contributor.author | 신찬수 | - |
dc.contributor.author | 박원규 | - |
dc.contributor.author | 송승철 | - |
dc.contributor.author | G.Yeap | - |
dc.contributor.author | R.Hill | - |
dc.contributor.author | C.Hobbs | - |
dc.contributor.author | W.Maszara | - |
dc.contributor.author | 김대현 | - |
dc.contributor.author | P.Kirsch | - |
dc.date.accessioned | 2018-05-24T11:24:03Z | - |
dc.date.available | 2018-05-24T11:24:03Z | - |
dc.date.created | 2017-02-23 | - |
dc.date.issued | 2014-06-09 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/49466 | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | International Symposium on VLSI Technology (VLSI2014) | - |
dc.relation.isPartOf | INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY DIGEST | - |
dc.title | Electrostatics and Performance Benchmarking using all Types of III-V Multi-Gate FinFETs for sub 7nm Technology Node Logic Application | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | International Symposium on VLSI Technology (VLSI2014) | - |
dc.citation.conferencePlace | US | - |
dc.citation.title | International Symposium on VLSI Technology (VLSI2014) | - |
dc.contributor.affiliatedAuthor | 백록현 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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