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dc.contributor.authorLI, DONG-
dc.contributor.authorRHU, MINSOO-
dc.contributor.authorJOHNSON, DANIEL-
dc.contributor.authorO'CONNOR, MIKE-
dc.contributor.authorEREZ, MATTAN-
dc.contributor.authorBURGER, DOUG-
dc.contributor.authorFUSSELL, DONALD-
dc.contributor.authorKECKLER, STEPHEN-
dc.date.accessioned2018-05-11T04:25:17Z-
dc.date.available2018-05-11T04:25:17Z-
dc.date.created2018-03-29-
dc.date.issued2015-02-09-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/43360-
dc.description.abstractGPUs employ massive multithreading and fast context switching to provide high throughput and hide memory latency. Multithreading can Increase contention for various system resources, however, that may result In suboptimal utilization of shared resources. Previous research has proposed variants of throttling thread-level parallelism to reduce cache contention and improve performance. Throttling approaches can, however, lead to under-utilizing thread contexts, on-chip interconnect, and off-chip memory bandwidth. This paper proposes to tightly couple the thread scheduling mechanism with the cache management algorithms such that GPU cache pollution is minimized while off-chip memory throughput is enhanced. We propose priority-based cache allocation (PCAL) that provides preferential cache capacity to a subset of high-priority threads while simultaneously allowing lower priority threads to execute without contending for the cache. By tuning thread-level parallelism while both optimizing caching efficiency as well as other shared resource usage, PCAL builds upon previous thread throttling approaches, improving overall performance by an average 17% with maximum 51%.-
dc.publisherIEEE-
dc.relation.isPartOfIEEE International Symposium on High Performance Computer Architecture-
dc.relation.isPartOfProceedings of the 21st IEEE International Symposium on High Performance Computer Architecture-
dc.titlePriority-Based Cache Allocation in Throughput Processors 
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dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitationIEEE International Symposium on High Performance Computer Architecture , pp.89 - 100-
dc.citation.conferenceDate2015-02-07-
dc.citation.conferencePlaceUS-
dc.citation.endPage100-
dc.citation.startPage89-
dc.citation.titleIEEE International Symposium on High Performance Computer Architecture-
dc.contributor.affiliatedAuthorRHU, MINSOO-
dc.description.journalClass1-
dc.description.journalClass1-

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유민수RHU, MINSOO
Dept of Computer Science & Enginrg
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