DC Field | Value | Language |
---|---|---|
dc.contributor.author | SIM, JAE YOON | - |
dc.contributor.author | Hwasuk Cho | - |
dc.contributor.author | Kihwan Seong | - |
dc.contributor.author | Kwang-Hee Choi | - |
dc.contributor.author | Jin-Hyeok Choi | - |
dc.contributor.author | Byungsub Kim | - |
dc.contributor.author | Hong-June Park | - |
dc.date.accessioned | 2018-05-10T23:03:42Z | - |
dc.date.available | 2018-05-10T23:03:42Z | - |
dc.date.created | 2018-02-06 | - |
dc.date.issued | 2017-02-07 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/42415 | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE International Solid-State Circuits Conference | - |
dc.relation.isPartOf | IEEE International Solid-State Circuits Conference | - |
dc.title | A 0.0047mm2 Highly Synthesizable TDC and DCO-less Fractional-NPLL with a Seamless Lock - Range off RER to 1GHz | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | IEEE International Solid-State Circuits Conference | - |
dc.citation.conferenceDate | 2017-02-05 | - |
dc.citation.conferencePlace | US | - |
dc.citation.conferencePlace | Sanfrancisco | - |
dc.citation.title | IEEE International Solid-State Circuits Conference | - |
dc.contributor.affiliatedAuthor | SIM, JAE YOON | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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