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Article

Memory-reduced turbo decoding architecture using NII metric compressionSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 63, no. 2, page. 211 - 215, 2016-02

Article

Low-power parallel Chien search architecture using a two-step approachSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 63, no. 3, page. 269 - 273, 2016-03

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