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Conference
Two-coupled 마이크로스트립 라인의 SPICE RLGC 파라미터 추출

2010 SoC학술대회, 2010-05-01

Conference
A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using A Three-Level Balanced Coding Scheme

IEEE Symposia on VLSI Technology and Circuits, 2016-06-15

Conference
A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using a Three-Level Balanced Coding Scheme

2016 Symposia on VLSI Technology and Circuits, 2016-06-15

Conference
A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using a Three-Level Balanced Coding Scheme

2016 Symposia on VLSI Technology and Circuits, 2016-06-15

Conference
A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

Society for Information Display 2010, page. 62 - 65, 2010-05-25

Conference
A Slew-Rate Controlled Transmitter to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines

IEEE Custom Integrated Circuits Conference, 2010-09-20

Conference
A Slew-Rate Controlled Transmitter to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines

Custom Integrated Circuits Conference, 2010-09-20

Conference
A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

SID Symposium Digest of Technical Papers, 2010-05-30

Conference
Two-coupled 마이크로스트립 라인의 SPICE RLGC 파라미터 추출

대한전자공학회 SoC 학술대회, 2010-05-01

Conference
A 27% Reduction in Transceiver Power for Single-Ended Point-to-Point DRAM Interface with the Termination Resistance of 4xZ0 at both TX and RX

IEEE International Solid-State Circuits Conference, page. 308 - 310, 2013-02-20

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