DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seong, Kihwan | - |
dc.contributor.author | Lee, Won-Cheol | - |
dc.contributor.author | Kim, Byungsub | - |
dc.contributor.author | SIM, JAE YOON | - |
dc.contributor.author | PARK, HONG JUNE | - |
dc.date.accessioned | 2018-01-04T11:27:44Z | - |
dc.date.available | 2018-01-04T11:27:44Z | - |
dc.date.created | 2017-08-22 | - |
dc.date.issued | 2016-06 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/39258 | - |
dc.description.abstract | A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies 0.038 mm(2), consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively. | - |
dc.language | English | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.relation.isPartOf | Journal of Semiconductor Technology and Science | - |
dc.title | All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0 | - |
dc.type | Article | - |
dc.identifier.doi | 10.5573/JSTS.2016.16.3.352 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | Journal of Semiconductor Technology and Science, v.16, no.3, pp.352 - 358 | - |
dc.identifier.wosid | 000379221100012 | - |
dc.date.tcdate | 2018-03-23 | - |
dc.citation.endPage | 358 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 352 | - |
dc.citation.title | Journal of Semiconductor Technology and Science | - |
dc.citation.volume | 16 | - |
dc.contributor.affiliatedAuthor | Lee, Won-Cheol | - |
dc.contributor.affiliatedAuthor | Kim, Byungsub | - |
dc.contributor.affiliatedAuthor | SIM, JAE YOON | - |
dc.contributor.affiliatedAuthor | PARK, HONG JUNE | - |
dc.identifier.scopusid | 2-s2.0-84977492207 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Multi-phase | - |
dc.subject.keywordAuthor | ring oscillator | - |
dc.subject.keywordAuthor | digitally controlled oscillator (DCO) | - |
dc.subject.keywordAuthor | phase-locked loop | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
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