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Cited 5 time in webofscience Cited 6 time in scopus
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dc.contributor.authorSeo, Jaehyun-
dc.contributor.authorLee, Sangheon-
dc.contributor.authorKim, Kwangmin-
dc.contributor.authorLee, Sooeun-
dc.contributor.authorHWANG, HYUNSANG-
dc.contributor.authorKim, Byungsub-
dc.date.accessioned2018-01-04T10:41:54Z-
dc.date.available2018-01-04T10:41:54Z-
dc.date.created2017-08-22-
dc.date.issued2017-02-
dc.identifier.issn1063-8210-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/39199-
dc.description.abstractThis paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our model generator automatically produces SPICE models of ReRAM devices and selectors from the measured I-V data to reduce too much time consumption in manual model development for ReRAM devices and simulation of the target ReRAM circuits. To verify our method, SPICE models for diverse ReRAMs were automatically generated from measured data and simulated with various circuits. The results show that our model can accurately describe the original data and allows fast quantitative evaluation of ReRAM circuits. Because developing SPICE models of ReRAMs and simulating them with circuits have been the critical time-consuming procedure in ReRAM research, these results show that our method enables early ReRAM evaluation.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.relation.isPartOfIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS-
dc.subjectAutomatic model generation-
dc.subjectresistive random access memory (ReRAM)-circuit cosimulation-
dc.subjectResistive Random Accesss Memory-
dc.subjectselector-
dc.subjectSPICE model-
dc.titleAutomatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation-
dc.typeArticle-
dc.identifier.doi10.1109/TVLSI.2017.2655730-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.6, pp.1821 - 1830-
dc.identifier.wosid000402137300003-
dc.date.tcdate2019-02-01-
dc.citation.endPage1830-
dc.citation.number6-
dc.citation.startPage1821-
dc.citation.titleIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS-
dc.citation.volume25-
dc.contributor.affiliatedAuthorSeo, Jaehyun-
dc.contributor.affiliatedAuthorKim, Kwangmin-
dc.contributor.affiliatedAuthorLee, Sooeun-
dc.contributor.affiliatedAuthorHWANG, HYUNSANG-
dc.contributor.affiliatedAuthorKim, Byungsub-
dc.identifier.scopusid2-s2.0-85011990279-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.wostc1-
dc.type.docTypeARTICLE-
dc.subject.keywordPlusRANDOM-ACCESS MEMORY-
dc.subject.keywordPlusSIMULATION-
dc.subject.keywordPlusDEVICE-
dc.subject.keywordAuthorAutomatic model generation-
dc.subject.keywordAuthorresistive random access memory (ReRAM)-circuit cosimulation-
dc.subject.keywordAuthorResistive Random Accesss Memory-
dc.subject.keywordAuthorselector-
dc.subject.keywordAuthorSPICE model-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-

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김병섭KIM, BYUNGSUB
Dept of Electrical Enginrg
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