DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seo, Jaehyun | - |
dc.contributor.author | Lee, Sangheon | - |
dc.contributor.author | Kim, Kwangmin | - |
dc.contributor.author | Lee, Sooeun | - |
dc.contributor.author | HWANG, HYUNSANG | - |
dc.contributor.author | Kim, Byungsub | - |
dc.date.accessioned | 2018-01-04T10:41:54Z | - |
dc.date.available | 2018-01-04T10:41:54Z | - |
dc.date.created | 2017-08-22 | - |
dc.date.issued | 2017-02 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/39199 | - |
dc.description.abstract | This paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our model generator automatically produces SPICE models of ReRAM devices and selectors from the measured I-V data to reduce too much time consumption in manual model development for ReRAM devices and simulation of the target ReRAM circuits. To verify our method, SPICE models for diverse ReRAMs were automatically generated from measured data and simulated with various circuits. The results show that our model can accurately describe the original data and allows fast quantitative evaluation of ReRAM circuits. Because developing SPICE models of ReRAMs and simulating them with circuits have been the critical time-consuming procedure in ReRAM research, these results show that our method enables early ReRAM evaluation. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.subject | Automatic model generation | - |
dc.subject | resistive random access memory (ReRAM)-circuit cosimulation | - |
dc.subject | Resistive Random Accesss Memory | - |
dc.subject | selector | - |
dc.subject | SPICE model | - |
dc.title | Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TVLSI.2017.2655730 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.6, pp.1821 - 1830 | - |
dc.identifier.wosid | 000402137300003 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 1830 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 1821 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 25 | - |
dc.contributor.affiliatedAuthor | Seo, Jaehyun | - |
dc.contributor.affiliatedAuthor | Kim, Kwangmin | - |
dc.contributor.affiliatedAuthor | Lee, Sooeun | - |
dc.contributor.affiliatedAuthor | HWANG, HYUNSANG | - |
dc.contributor.affiliatedAuthor | Kim, Byungsub | - |
dc.identifier.scopusid | 2-s2.0-85011990279 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 1 | - |
dc.type.docType | ARTICLE | - |
dc.subject.keywordPlus | RANDOM-ACCESS MEMORY | - |
dc.subject.keywordPlus | SIMULATION | - |
dc.subject.keywordPlus | DEVICE | - |
dc.subject.keywordAuthor | Automatic model generation | - |
dc.subject.keywordAuthor | resistive random access memory (ReRAM)-circuit cosimulation | - |
dc.subject.keywordAuthor | Resistive Random Accesss Memory | - |
dc.subject.keywordAuthor | selector | - |
dc.subject.keywordAuthor | SPICE model | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
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