DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ji-Hoon Lim | - |
dc.contributor.author | Jun-Hyun Bae | - |
dc.contributor.author | Jaemin Jang | - |
dc.contributor.author | Hae-Kang Jung | - |
dc.contributor.author | Hyunbae Lee | - |
dc.contributor.author | Yongju Kim | - |
dc.contributor.author | Byungsub Kim | - |
dc.contributor.author | Sim, JY | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2017-07-19T12:32:03Z | - |
dc.date.available | 2017-07-19T12:32:03Z | - |
dc.date.created | 2016-02-18 | - |
dc.date.issued | 2016-02 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/35984 | - |
dc.description.abstract | A feedback edge combiner is proposed for the duty-cycle corrector (DCC) of a delay locked loop (DLL) to increase the range of allowed input duty cycle. The feedback edge combiner generates the rising edge of a DCC output at the rising edge of an input clock. It generates the falling edge of the DCC output at the rising edge of a feedback clock that is a half-period-delayed signal of the DCC output. A dual-delay-line digitally controlled delay line (DCDL) is used for seamless boundary switching. The chip area of the DCDL is reduced by around 46% by employing the architecture of two short coarse delay lines followed by a fine phase mixer (FPM) and a long coarse delay line in series instead of the architecture of two long coarse delay lines followed by an FPM. The measurements on the chip fabricated in the 65-nm CMOS show the allowed input duty cycle in the range from 20% to 80%; root-mean-square and peak-to-peak jitters of 2.69 and 14.0 ps, respectively, at 2 GHz and 1.2 V; and the operating frequency range from 0.12 to 2.0 GHz at 1.2 V. The measured power consumption is 3.3 mW/GHz at 1.2 V. The chip area is 0.059 mm(2). | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS | - |
dc.title | A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TCSII.2015.2468911 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, v.63, no.2, pp.141 - 145 | - |
dc.identifier.wosid | 000370533000005 | - |
dc.date.tcdate | 2019-03-01 | - |
dc.citation.endPage | 145 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 141 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS | - |
dc.citation.volume | 63 | - |
dc.contributor.affiliatedAuthor | Ji-Hoon Lim | - |
dc.contributor.affiliatedAuthor | Sim, JY | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.identifier.scopusid | 2-s2.0-84962243263 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 12 | - |
dc.description.isOpenAccess | N | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Delay locked loop (DLL) | - |
dc.subject.keywordAuthor | DDR type 4 (DDR4) | - |
dc.subject.keywordAuthor | double date rate (DDR) type 3 (DDR3) | - |
dc.subject.keywordAuthor | duty-cycle corrector (DCC) | - |
dc.subject.keywordAuthor | feedback edge combiner | - |
dc.subject.keywordAuthor | fine phase mixer (FPM) | - |
dc.subject.keywordAuthor | synchronous dynamic random access memory (SDRAM) | - |
dc.subject.keywordAuthor | wide range | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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