Highly linear 0.18-mu m CMOS power amplifier with deep n-well structure

Abstract

The linearity of a 0.18-mu m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C-gs), which is the dominant nonlinear source, and partially from drain junction capacitance (C-jd)- Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-mu m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBrn of P-out, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P-1dB. The IMD3 and IMD5 are below -40 dBc and -47 dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P-out, 18.9 dB of power gain and 35% of PAE at P-1dB. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.