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Cited 5 time in webofscience Cited 9 time in scopus
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dc.contributor.authorSUNG, JH-
dc.date.accessioned2016-04-01T01:01:44Z-
dc.date.available2016-04-01T01:01:44Z-
dc.date.created2009-02-28-
dc.date.issued1990-03-
dc.identifier.issn0018-9340-
dc.identifier.other1990-OAK-0000008423-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/22306-
dc.description.statementofresponsibilityX-
dc.languageEnglish-
dc.publisherIEEE COMPUTER SOC-
dc.relation.isPartOfIEEE TRANSACTIONS ON COMPUTERS-
dc.titleTHE DESIGN OF A TESTABLE PARALLEL MULTIPLIER-
dc.typeArticle-
dc.contributor.college컴퓨터공학과-
dc.identifier.doi10.1109/12.48874-
dc.author.googleSUNG, JH-
dc.relation.volume39-
dc.relation.startpage411-
dc.relation.lastpage416-
dc.contributor.id10157751-
dc.relation.journalIEEE TRANSACTIONS ON COMPUTERS-
dc.relation.indexSCI급, SCOPUS 등재논문-
dc.relation.sciSCI-
dc.collections.nameJournal Papers-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON COMPUTERS, v.39, no.3, pp.411 - 416-
dc.identifier.wosidA1990CP59400014-
dc.citation.endPage416-
dc.citation.number3-
dc.citation.startPage411-
dc.citation.titleIEEE TRANSACTIONS ON COMPUTERS-
dc.citation.volume39-
dc.contributor.affiliatedAuthorSUNG, JH-
dc.identifier.scopusid2-s2.0-0025404741-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.wostc0-
dc.type.docTypeLetter-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-

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홍성제HONG, SUNG JE
Div of IT Convergence Enginrg
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