State minimisation-based loop handling for critical path analysis
SCIE
SCOPUS
- Title
- State minimisation-based loop handling for critical path analysis
- Authors
- Han, SY; Kim, YH
- Date Issued
- 1996-01-04
- Publisher
- IEE-INST ELEC ENG
- Abstract
- The authors present a new approach to the critical path analysis of digital circuits with feedback loops. The idea is to first convert a circuit with feedback loops to an equivalent minimum-sized acyclic circuit using a slate-minimisation technique of sequential machines and then to perform critical path analysis. The results of experiments illustrate that the proposed method finds critical paths correctly and efficiently in the presence of feedback loops.
- Keywords
- digital circuits; VLSI; MOS VLSI; CIRCUITS
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/21645
- DOI
- 10.1049/el:19960021
- ISSN
- 0013-5194
- Article Type
- Article
- Citation
- ELECTRONICS LETTERS, vol. 32, no. 1, page. 8 - 9, 1996-01-04
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- There are no files associated with this item.
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