Performance of single-electron transistor logic composed of multi-gate single-electron transistors

Abstract

We have performed Monte Carlo studies of complementary capacitively coupled single-electron transistor (complementary C-SET) logic gates for single-electron digital logic circuits. The simulations carried out with various types of complementary C-SET logic gates showed that serial connections of single-electron transistors necessary for multi-input operations resulted in the degradation of the switching speed. It is pointed out that the multi-gate single-electron transistor configuration can provide a possible means to circumvent this problem. However, the associated nonsymmetric input-output characteristics could cause the operation failure of the circuit. It is shown that the multi-gate single-electron transistor circuits are the optimal choice from the standpoint of high speed operation and design simplicity, when confined to the input voltages not exceeding four terminals.