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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, D | - |
| dc.contributor.author | Woo, J | - |
| dc.contributor.author | Cha, E | - |
| dc.contributor.author | Park, S | - |
| dc.contributor.author | Lee, S | - |
| dc.contributor.author | Park, J | - |
| dc.contributor.author | Hwang, H | - |
| dc.date.accessioned | 2016-03-31T08:16:09Z | - |
| dc.date.available | 2016-03-31T08:16:09Z | - |
| dc.date.created | 2014-03-03 | - |
| dc.date.issued | 2013-10 | - |
| dc.identifier.issn | 0741-3106 | - |
| dc.identifier.other | 2013-OAK-0000029030 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/14930 | - |
| dc.description.abstract | To develop a low-power and stable resistive RAM, a defect engineering using bilayer structure is proposed. To control the amount of defect in switching layer, interfacial state between an oxygen absorption layer and switching layer is used. Therefore, in low-power operation, defect engineered sample demonstrated the proposed approach based on its improved ON/OFF ratio and stability. | - |
| dc.description.statementofresponsibility | X | - |
| dc.language | English | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.relation.isPartOf | IEEE Electron Device Letters | - |
| dc.subject | Bilayer | - |
| dc.subject | defect engineering | - |
| dc.subject | interface engineering | - |
| dc.subject | low-power operation | - |
| dc.subject | resistive random access memory (RRAM) | - |
| dc.subject | MODEL | - |
| dc.title | Defect Engineering Using Bilayer Structure in Filament-Type RRAM | - |
| dc.type | Article | - |
| dc.contributor.college | 신소재공학과 | - |
| dc.identifier.doi | 10.1109/LED.2013.2279009 | - |
| dc.author.google | Lee, D | - |
| dc.author.google | Woo, J | - |
| dc.author.google | Cha, E | - |
| dc.author.google | Park, S | - |
| dc.author.google | Lee, S | - |
| dc.author.google | Park, J | - |
| dc.author.google | Hwang, H | - |
| dc.relation.volume | 34 | - |
| dc.relation.issue | 10 | - |
| dc.relation.startpage | 1250 | - |
| dc.relation.lastpage | 1252 | - |
| dc.contributor.id | 10079928 | - |
| dc.relation.journal | IEEE Electron Device Letters | - |
| dc.relation.index | SCI급, SCOPUS 등재논문 | - |
| dc.relation.sci | SCI | - |
| dc.collections.name | Journal Papers | - |
| dc.type.rims | ART | - |
| dc.identifier.bibliographicCitation | IEEE Electron Device Letters, v.34, no.10, pp.1250 - 1252 | - |
| dc.identifier.wosid | 000325186600015 | - |
| dc.date.tcdate | 2019-01-01 | - |
| dc.citation.endPage | 1252 | - |
| dc.citation.number | 10 | - |
| dc.citation.startPage | 1250 | - |
| dc.citation.title | IEEE Electron Device Letters | - |
| dc.citation.volume | 34 | - |
| dc.contributor.affiliatedAuthor | Hwang, H | - |
| dc.identifier.scopusid | 2-s2.0-84884818730 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
| dc.description.wostc | 9 | - |
| dc.description.scptc | 8 | * |
| dc.date.scptcdate | 2018-05-121 | * |
| dc.type.docType | Article | - |
| dc.subject.keywordAuthor | Bilayer | - |
| dc.subject.keywordAuthor | defect engineering | - |
| dc.subject.keywordAuthor | interface engineering | - |
| dc.subject.keywordAuthor | low-power operation | - |
| dc.subject.keywordAuthor | resistive random access memory (RRAM) | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
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