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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Woo, J | - |
| dc.contributor.author | Lee, D | - |
| dc.contributor.author | Cha, E | - |
| dc.contributor.author | Lee, S | - |
| dc.contributor.author | Park, S | - |
| dc.contributor.author | Hwang, H | - |
| dc.date.accessioned | 2016-03-31T08:16:05Z | - |
| dc.date.available | 2016-03-31T08:16:05Z | - |
| dc.date.created | 2014-03-03 | - |
| dc.date.issued | 2013-12 | - |
| dc.identifier.issn | 0741-3106 | - |
| dc.identifier.other | 2013-OAK-0000029032 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/14928 | - |
| dc.description.abstract | In this letter, we discuss our technique for fabricating a vertically stacked ReRAM device composed of one selector and one resistor (1S-1R). We demonstrate that the nanoscale via-hole structure and 1-kb array architecture of selector device exhibit higher current density (similar to 10(7) A/cm(2)) and reliability, and we introduce bipolar resistive switching element-a conductive-bridge RAM that can be stacked on top of the selector device. The resulting integrated 1S-1R device performs robust bipolar switching operations and significantly reduces the leakage current in cross-point applications. | - |
| dc.description.statementofresponsibility | X | - |
| dc.language | English | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.relation.isPartOf | IEEE Electron Device Letters | - |
| dc.subject | Cross-point array architecture | - |
| dc.subject | one selector and one resistor (1S-1R) | - |
| dc.subject | selector device | - |
| dc.subject | MEMORY | - |
| dc.title | Vertically Stacked ReRAM Composed of a Bidirectional Selector and CB-RAM for Cross-point Array Applications | - |
| dc.type | Article | - |
| dc.contributor.college | 신소재공학과 | - |
| dc.identifier.doi | 10.1109/LED.2013.2285583 | - |
| dc.author.google | Woo, J | - |
| dc.author.google | Lee, D | - |
| dc.author.google | Cha, E | - |
| dc.author.google | Lee, S | - |
| dc.author.google | Park, S | - |
| dc.author.google | Hwang, H | - |
| dc.relation.volume | 34 | - |
| dc.relation.issue | 12 | - |
| dc.relation.startpage | 1512 | - |
| dc.relation.lastpage | 1514 | - |
| dc.contributor.id | 10079928 | - |
| dc.relation.journal | IEEE Electron Device Letters | - |
| dc.relation.index | SCI급, SCOPUS 등재논문 | - |
| dc.relation.sci | SCI | - |
| dc.collections.name | Journal Papers | - |
| dc.type.rims | ART | - |
| dc.identifier.bibliographicCitation | IEEE Electron Device Letters, v.34, no.12, pp.1512 - 1514 | - |
| dc.identifier.wosid | 000327640400016 | - |
| dc.date.tcdate | 2019-01-01 | - |
| dc.citation.endPage | 1514 | - |
| dc.citation.number | 12 | - |
| dc.citation.startPage | 1512 | - |
| dc.citation.title | IEEE Electron Device Letters | - |
| dc.citation.volume | 34 | - |
| dc.contributor.affiliatedAuthor | Hwang, H | - |
| dc.identifier.scopusid | 2-s2.0-84889636339 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
| dc.description.wostc | 15 | - |
| dc.description.scptc | 12 | * |
| dc.date.scptcdate | 2018-05-121 | * |
| dc.type.docType | Article | - |
| dc.subject.keywordAuthor | Cross-point array architecture | - |
| dc.subject.keywordAuthor | one selector and one resistor (1S-1R) | - |
| dc.subject.keywordAuthor | selector device | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
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