DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, M | - |
dc.contributor.author | Sim, JY | - |
dc.contributor.author | Park, HJ | - |
dc.contributor.author | Kim, B | - |
dc.date.accessioned | 2016-03-31T07:36:28Z | - |
dc.date.available | 2016-03-31T07:36:28Z | - |
dc.date.created | 2015-02-04 | - |
dc.date.issued | 2014-10 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.other | 2014-OAK-0000031729 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/13816 | - |
dc.description.abstract | This paper presents an approximate closed-form channel model for a wide range of high-speed interconnect designs. Closed-form formulas derived from telegrapher's equation can accurately describe frequency responses of various interconnects, which have hardly been described by simple closed-form formulas, as long as the channels meet clear validity conditions. The formulas also provide a simple and intuitive equivalent circuit representation which allows designers to separately consider the effects of transmitter impedance, receiver termination, and wire attenuation. For a wide range of applications, the relative error of our model is theoretically bounded by the validity conditions. The model's accuracy is verified by comparing the calculated transfer functions against simulation results using the previous method built in SPICE for various interconnect examples from LC-dominant printed-circuit-board interconnects to RC-dominant silicon-interposer interconnects. In addition, the simplicity of our model improves computation time by about 162 times compared to the previous numerical computation method. With this channel model, designers can intuitively and accurately analyze the behavior of interconnects and design trade-offs of a wide range of interconnects without complex numerical simulation. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.subject | Interconnect model | - |
dc.subject | printed circuit board | - |
dc.subject | signal integrity | - |
dc.subject | silicon interposer | - |
dc.subject | transmission line | - |
dc.subject | TRANSMISSION-LINES | - |
dc.subject | TRANSCEIVER | - |
dc.subject | DESIGN | - |
dc.subject | PERFORMANCE | - |
dc.subject | SIMULATION | - |
dc.subject | CIRCUITS | - |
dc.subject | WIRES | - |
dc.subject | I/O | - |
dc.title | An Approximate Closed-Form Channel Model for Diverse Interconnect Applications | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.1109/TCSI.2014.2327275 | - |
dc.author.google | Choi, M | - |
dc.author.google | Sim, JY | - |
dc.author.google | Park, HJ | - |
dc.author.google | Kim, B | - |
dc.relation.volume | 61 | - |
dc.relation.issue | 10 | - |
dc.relation.startpage | 3034 | - |
dc.relation.lastpage | 3043 | - |
dc.contributor.id | 11082511 | - |
dc.relation.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCI | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.10, pp.3034 - 3043 | - |
dc.identifier.wosid | 000343003100029 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 3043 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 3034 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 61 | - |
dc.contributor.affiliatedAuthor | Sim, JY | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.contributor.affiliatedAuthor | Kim, B | - |
dc.identifier.scopusid | 2-s2.0-84907601422 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 7 | - |
dc.description.scptc | 5 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.type.docType | Article | - |
dc.subject.keywordPlus | TRANSMISSION-LINES | - |
dc.subject.keywordPlus | TRANSCEIVER | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | SIMULATION | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | I/O | - |
dc.subject.keywordAuthor | Interconnect model | - |
dc.subject.keywordAuthor | printed circuit board | - |
dc.subject.keywordAuthor | signal integrity | - |
dc.subject.keywordAuthor | silicon interposer | - |
dc.subject.keywordAuthor | transmission line | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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