DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ki-Hwan Seong | - |
dc.contributor.author | Ji-Hoon Lim | - |
dc.contributor.author | Kim, B | - |
dc.contributor.author | Sim, JY | - |
dc.contributor.author | Park, HJ | - |
dc.date.accessioned | 2016-03-31T07:30:14Z | - |
dc.date.available | 2016-03-31T07:30:14Z | - |
dc.date.created | 2015-02-09 | - |
dc.date.issued | 2014-08 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.other | 2014-OAK-0000032042 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/13703 | - |
dc.description.abstract | A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit. | - |
dc.description.statementofresponsibility | X | - |
dc.language | English | - |
dc.publisher | 대한전자공학회 | - |
dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.title | Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface | - |
dc.type | Article | - |
dc.contributor.college | 전자전기공학과 | - |
dc.identifier.doi | 10.5573/JSTS.2014.14.4.463 | - |
dc.author.google | Seong, KH | - |
dc.author.google | Lim, JH | - |
dc.author.google | Kim, B | - |
dc.author.google | Sim, JY | - |
dc.author.google | Park, HJ | - |
dc.relation.volume | 14 | - |
dc.relation.issue | 4 | - |
dc.relation.startpage | 463 | - |
dc.relation.lastpage | 470 | - |
dc.contributor.id | 11082511 | - |
dc.relation.journal | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.relation.index | SCI급, SCOPUS 등재논문 | - |
dc.relation.sci | SCIE | - |
dc.collections.name | Journal Papers | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.14, no.4, pp.463 - 470 | - |
dc.identifier.wosid | 000346136600013 | - |
dc.date.tcdate | 2019-01-01 | - |
dc.citation.endPage | 470 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 463 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 14 | - |
dc.contributor.affiliatedAuthor | Kim, B | - |
dc.contributor.affiliatedAuthor | Sim, JY | - |
dc.contributor.affiliatedAuthor | Park, HJ | - |
dc.identifier.scopusid | 2-s2.0-84906887829 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 3 | - |
dc.description.scptc | 3 | * |
dc.date.scptcdate | 2018-05-121 | * |
dc.description.isOpenAccess | Y | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Verilog | - |
dc.subject.keywordAuthor | transmission line | - |
dc.subject.keywordAuthor | USB 2.0 high-speed PHY | - |
dc.subject.keywordAuthor | mixed-mode simulation | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
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