Reduction of reflection in 8-drop DRAM channel and a low power DRAM controller with large termination resistance of I/O driver

Abstract

Two schemes are proposed for high-speed and low-power DRAM interface in this thesis. For high-speed DRAM interface, an 8-drop parallel branching SDRAM channel with write-direction impedance-matching (PBIM) is proposed. The PBIM channel achieved a high-speed operation by reducing write-direction reflection. The 8-drop PBIM channel consists of two parallel branches; each branch consists of a series connection of 2 DIMMs for a 4-drop configuration, two kinds of transmission lines with characteristic impedances of 50 and 25 ohms and a resistor on motherboard for a data (DQ) channel. Measurements on the test setup show that the proposed 8-drop channel works at the DDR5 target data rate of 6.4 Gbps with the bit error rate less than 1E-12 in both write and read directions by using the same-area motherboard area as stub series terminated logic (SSTL) channel. For low-power DRAM interface, a DRAM controller ASIC with large termination resistance of I/O driver is proposed. The termination resistance of the DRAM controller is increased to 160 Ω and infinity during the write and read modes, respectively, to reduce power with no transmission errors. Short-reach interconnects of 25 mm DQ/DQS lines are used to avoid the signal integrity issues. The proposed DRAM controller ASIC is implemented in a 65 nm process with an active area of 1.64 mm2, 16 DQ 8 Gb configuration, and a data rate of 800 Mbps per DQ pin. The DRAM interface using the proposed DRAM controller ASIC and commercial DDR3 DRAM chip consumes 379 mW on average; this is 64% of the power with the default termination of the JEDEC standard. Derived equations for the TX and RX current of the DRAM interface reveals that the current of a clock driver is minimized when the time of flight of the PCB channel is integer multiples ofthe half period of the clock signal with the large TX and RX terminations.