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Subject : PLL

Article

A 26GHz Fractional-N Digital Frequency Synthesizer Leveraging Noise Profiles of Three Functional StagesSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 68, no. 9, page. 3063 - 3067, 2021-09

Article

A Phase-Interpolator based Fractional-Counter for All Digital Fractional-N Phase-Locked LoopSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 61, no. 3, page. 249 - 253, 2017-03

Article

A 250μW 2.4GHz Fast-Lock Fractional-N Frequency Generation for Ultra-Low-Power ApplicationsSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 64, no. 2, page. 106 - 110, 2017-02

Article

A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded SignalingSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, vol. 63, no. 4, page. 482 - 493, 2016-04

Article

Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor PlatformSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 50, no. 5, page. 1263 - 1274, 2015-05

Article

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 mu m CMOSSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 45, no. 12, page. 2874 - 2881, 2010-12

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