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Real-Time Pedestrian Detection in 60 fps Video on FPGA

Title
Real-Time Pedestrian Detection in 60 fps Video on FPGA
Authors
김병준
Date Issued
2018
Publisher
포항공과대학교
Abstract
This paper presents a real-time pedestrian detection hardware architecture on Field Programmable Gate Arrays (FPGAs). This architecture uses Histograms of Oriented Gradients (HOG) descriptor and Support Vector Machine (SVM) for classifier. We designed a norm and arctangent calculator, using a formula of trigonometric function leading to low loss of detection rate and high efficiency of resource usage. HOG modules of all scales share SVM module, this design uses resources efficiently. We could process 60 images (1024 x 768 pixels) per second at 10 scales with a latency of < 200 μs. We could apply this hardware system to many areas including self-driving cars, autonomous robot navigation.
URI
http://postech.dcollection.net/common/orgView/200000009550
https://oasis.postech.ac.kr/handle/2014.oak/93355
Article Type
Thesis
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