A Study on Digital Quadrature RF Transmitter for Mobile Communication Systems

Abstract

This thesis proposed and designed digitally configured versatile RF quadrature transmitters. Due to the digital circuit's nature, it has excellent programmability, making it suitable for SDR applications. It is also easier to integrate the transmitter as a system-on-a-chip with non-RF circuits such as modem and application processor, which are full digital circuits. The quadrature transmitter does not require the CORDIC so is simple and requires low computing cost. This advantage can have a significant impact on the communication system having a large signal bandwidth. Due to these advantageous characteristics, the quadrature transmitters have been studied in order to eliminate the cumbersome CORDIC. For an efficient digital quadrature transmitter employing RF DACs, with an array of class-D PA and a capacitor power combiner, directly generated RF signal from baseband digital I and Q signals. By applying a deactivate opposite cell technique, the digital transmitter delivers high efficiency and good linearity. The measured drain efficiencies and total efficiencies of the implemented transmitter are 14.4/10.6% and 10.8/6.3% at peak output power of 7.87/-0.11 dBm for CW/LTE 10-MHz signals, respectively. As the eliminating the 3-dB power summation loss among I and Q cells, the digital quadrature transmitter efficiency is enhanced by IQ cell sharing and deactivating opposite cells. These techniques can simulate the average efficiency of the transmitter for the 6.9 dB LTE signal to increase it from 46.3% to 70.7%. In addition, the number of power amplifying cells is reduced by half, improving the total efficiency of the transmitter. The proposed transmitter is implemented and verified in the 6-bit digital transmitter for the 0.8 GHz application using a 28-nm CMOS process. The dynamic range of the measured output power is from -20.2 dBm to 13.9 dBm, and the measured average output power is 6.97 dBm using 6.9 dB LTE signal. The power-added efficiencies (PAE) of the transmitter at the peak power and average power are 40.43% and 29.1%, respectively. To reduce the C/D loss which is caused when I or Q is a larger value than its quadrant value (Q or I), the cell in the DCS transmitter is dynamically selected to minimize the voltage across the capacitors, thereby minimizing the discharging loss. The chip is fabricated in 28-nm CMOS process. The implemented transmitter has a peak power of 17.2 dBm with a PAE of 37.4% at 880 MHz. The average power is 7.9 dBm with a PAE of 23.6% under ACLR of -32 dBc using a 10 MHz, 16 QAM, and 6.9 dB LTE signal. This paper presents a digital quadrature dual VDD transmitter with a switched capacitor power combiner. To reduce the C/D loss in the stacked structure, the new mapping technique reduces the voltage differences among the capacitors. The structure has lower C/D loss by reducing the voltage difference and two peak efficiencies at the 6dB back-off power and the peak power, boosting the efficiency. We propose a new mapping technique which is optimized to the IQ sharing structure with dual VDD to maximize the efficiency and output power. The peak power of the proposed transmitter with minimized C/D loss is 24.9 dBm with 56.3% efficiency. For 10MHz bandwidth LTE signal with 6.9 dB PAPR, the average efficiency and power are 39.4% and 14.4 dBm, respectively. ACLRs are under -36 dBc.