A Phase-Interpolator based Fractional-Counter for All Digital Fractional-N PLL and A 6Gbps All Synthesizable Transceiver with TX FFE and RX DFE
- A Phase-Interpolator based Fractional-Counter for All Digital Fractional-N PLL and A 6Gbps All Synthesizable Transceiver with TX FFE and RX DFE
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- In this thesis, a phase-interpolator based fractional-counter for all digital fractional-N PLL and a 6 Gbps all synthesizable transceiver with TX FFE and RX DFE are proposed.
Firstly, a phase-interpolator-based fractional counter (PIFC) is proposed to reduce power consumption by replacing TDC in a ring-oscillator-based digital fractional-N phase-locked-loop. A predicted-phase-interpolation method is used to calculate the integer and fractional parts of the frequency-division-ratio and to find two interpolation clocks; the prediction method gives a significant power reduction in the proposed PIFC by enabling the use of low frequency clocks for phase interpolation. The proposed PLL chip in a 65 nm CMOS occupies 0.173 mm2 and consumes 15.5 mW at 6 GHz and 1.2 V; the PIFC consumes less than 20% of the TDC power. The integrated RMS jitter is 1.75 ps and FoM value of -223.2 dB is achieved.
Secondly, all synthesizable transmitter (TX) and receiver (RX) circuit is proposed. The proposed TX and RX consist of digital standard library cells. In the proposed transceiver, 2-tap feed-forward equalizer (FFE) and 1-tap decision-feedback equalizer (DFE) are employed to compensate inter-symbol-interference (ISI) at TX and RX, respectively. A DLL which generates 1-bit period delayed signal for TX FFE is employed to overcome speed limitation of D flip-flop in standard library. The proposed transceiver chip in a 65 nm CMOS technology works at 6 Gbps with a 1.4m FR4 micro-strip line. The DFE achieve 20% improvement in the timing margin with BER < 10-12. The power consumption is 33.6 mW and 7.2 mW with a 1.2 V supply at TX and RX, respectively.
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