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A 2 GHz Synthesized Fractional-N ADPLL with Dual-Referenced Interpolating TDC

Title
A 2 GHz Synthesized Fractional-N ADPLL with Dual-Referenced Interpolating TDC
Authors
김신웅
Date Issued
2016
Publisher
포항공과대학교
Abstract
This thesis presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating TDC. The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage and temperature variations by averaging nonlinearity errors of opposite polarities. Except for DCO, the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of 0.047 mm2 and achieves a stable in-band phase noise of lower than -100 dBc/Hz in a wide range of supply voltage from 1 to 1.4 V.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002228212
http://oasis.postech.ac.kr/handle/2014.oak/93230
Article Type
Thesis
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